planar transistor
英 [ˈpleɪnə(r) trænˈzɪstə(r)]
美 [ˈpleɪnər trænˈzɪstər]
平面晶体管
双语例句
- At present, leading-edge chip makers are using conventional bulk CMOS and planar transistor structures for the32-/ 28-nm nodes.
目前制造晶体管的主流技术是采用体硅技术制作的32/28nm制程平面型晶体管。 - A planar SiGe heterojunction bipolar transistor was fabricated using polysilicon emitter technology and SiGe base grown by Molecular Beam Epitaxy ( MBE).
利用多晶硅发射极技术与分子束外延生长SiGe基区技术相结合，研制成适于集成的平面结构、发射结面积为3μm×8μm的SiGe异质结双极晶体管（HBT）。 - By using linear E f n s approximation, a new analytical charge control model of the double heterojunction double planar doped high electron mobility transistor ( HEMT) is deduced based on Poisson's equation.
利用泊松方程以及异质结能带理论，通过费米能级-二维电子气浓度的线性近似，推导了基于双异质结双平面掺杂的HEMT器件的电荷控制模型。 - With the increasing of device density in the integrated circuit, the issues of the power dissipation in the conventional planar metal oxide semiconductor field effect transistor ( MOSFET) become more prominent.
随着集成电路中器件密度的增加，传统平面MOS晶体管（MOSFET）的功耗问题变得更加突出。